tech
Huawei's 'chip queen' unveils Tau Scaling Law
Huawei’s semiconductor chief He Tingbo returned to public life after seven years to unveil the Tau Scaling Law and LogicFolding architecture. The company claims it can reach 1.4nm-equivalent chip density by 2031 without EUV lithography, but faces steep hurdles in heat dissipation, EDA tooling, and yield rates.
TL;DR
- He Tingbo, head of Huawei's semiconductor business, has introduced the "Tau (τ) Scaling Law" and "LogicFolding" architecture.
- The Tau Scaling Law replaces geometric shrinking with signal-propagation time as the metric for progress in semiconductors.
- Huawei claims this new approach will allow them to achieve transistor densities equivalent to a 1.4nm process by 2031, without using EUV lithography machines blocked by US sanctions.
- The LogicFolding architecture is a proprietary design that vertically stacks circuit layouts, increasing transistor density.
- While hailed as a breakthrough, analysts note that elements of this approach, like Design-Technology Co-Optimisation, are not entirely new.
- Huawei's efforts are seen as a response to US sanctions, demonstrating a strategy of constraint driving innovation.
- Challenges remain, including managing increased heat density, developing compatible EDA tools, and achieving commercially viable yield rates for stacked layers.
- Nvidia CEO Jensen Huang has acknowledged Huawei's progress but expressed concerns about its implications for the US market.
- The success of the Tau Scaling Law and LogicFolding will be tested with upcoming commercial releases, particularly in Huawei's next-generation smartphones.