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Huawei Unveils Tau Scaling Law for Next-Gen Chip Evolution
Huawei is launching 3D LogicFolding tech to boost transistor density as Moore’s Law hits limits in modern chip design
TL;DR
- Moore's Law is facing physical limitations, prompting the semiconductor industry to seek new guiding principles.
- Huawei has proposed the Tau Scaling Law, which prioritizes shortening signal transmission times over transistor shrinking.
- The core technology for this law is LogicFolding, a method that reconfigures chip architecture from 2D to 3D.
- LogicFolding involves layering planar circuits vertically, reducing signal path lengths and data bottlenecks.
- This 3D approach enhances transistor density, speed, and energy efficiency through multi-level co-optimization.
- Huawei has already developed 381 chips based on the Tau Scaling Law and plans to integrate LogicFolding into its Kirin chips in autumn 2026.
- By 2031, Huawei expects chips based on this law to achieve transistor densities equivalent to 1.4 nm processes.